Chip warpage and stress analysis in power modules of different substrate configurations

Abstract

Purpose

This paper aims to use rigorous finite element simulations to investigate the impact of different substrate systems on the warpage behavior of silicon (Si) chips of power modules exposed to thermal loading.

Design/methodology/approach

Three common substrate systems: direct copper bonded (DCB), insulated metal substrate (IMS) and printed circuit board (PCB) configurations examined. In addition, three lead-free bonding materials: silver-tin transient liquid phase (TLP), sintered silver (Ag) and sintered copper (Cu). This results in nine assembly configurations. Finite element models of the electronic modules are developed using ANSYS to apply thermal loads from room temperature to 250°C to induce deformations, strains and stresses in the electronic structure. Accordingly, the silicon chip deformations and maximum principal stresses of each assembly configuration are thoroughly examined.

Findings

The results indicate that DCB-based power modules markedly reduce Si die warpage and maximum principal stresses, suggesting enhanced resistance to thermal loads. In contrast, IMS systems exhibit the highest levels of die warpage and out-of-plane deformation. PCB substrates, however, induce the highest maximum principal stress values in the silicon die, potentially leading to accelerated crack initiation and propagation. While the die attach system has a minimal effect on die warpage, the silver-tin TLP bonds generate significantly higher die stresses compared with sintered Ag and sintered Cu, which both result in reduced stresses.

Originality/value

Power electronics exceptionally rely on ceramic-based and polymer-based substrate systems due to their superior thermal conductivity, heat resistance and electrical insulation properties. The strategic selection of substrate structures can significantly enhance the robustness of power. Ultimately, the findings of this research provide valuable insights for the design of highly reliable and efficient power modules subjected to thermal stress.

Citation

Gharaibeh, M.A. (2025), "Chip warpage and stress analysis in power modules of different substrate configurations", Soldering & Surface Mount Technology, Vol. ahead-of-print No. ahead-of-print. https://doi.org/10.1108/SSMT-11-2024-0069