Simulation of Assembly Generated Constraints on Ceramic Capacitors during SMT Processing and Size Optimisation of the Capacitors by Design of Experiments

Abstract

Present‐day electronics are shifting increasingly towards surface mounting technology (SMT) and hybrid technology (thick and thin film), which offer greater advantages due to their fabrication processes. Capacitors, like other components used in these processes, must occupy the smallest volume possible. Because of miniaturisation of the capacitors, the reliability of the surface mounting process is affected not only by the reliability of the components themselves but also by that of the assembly. In this study, a thermo‐mechanical simulation has been performed by means of ANSYS software based on the finite element method. This paper deals with the evaluation of a ceramic capacitor module (capacitors soldered on copper lands) on FR‐4 or alumina substrates during cooling to room temperature (25°C). The parameters of the assembly — temperature, length and thickness of the capacitor, thickness of the solder joint and nature of the substrate — were chosen by using the Design Of Experiments (DOE) method, which permits optimisation of these parameters and reduces the investigation time. The results showed a correlation between the length of the capacitor and the nature of the substrate used. Greater capacitor length is required for alumina substrate while a shorter length is preferred for FR‐4. It appears that a solder joint more than 100 urn thick may induce significant constraints on the copper lands and on the capacitor leads. It was noted that shear stress and voids in the solder joint can occur at temperatures higher than 250°C. This investigation makes it possible to prevent thermo‐mechanical stress damage during the mounting process and gives some recommendations for the choice of assembly variables.

Citation

Ousten, Y., Bechou, L. and Xiong, N. (1993), "Simulation of Assembly Generated Constraints on Ceramic Capacitors during SMT Processing and Size Optimisation of the Capacitors by Design of Experiments", Microelectronics International, Vol. 10 No. 3, pp. 26-32. https://doi.org/10.1108/eb044510