Report on the Institute of Circuit Technology 27th Annual Symposium – 2001 Printed Circuit Odyssey

Citation

Starkey, P. (2001), "Report on the Institute of Circuit Technology 27th Annual Symposium – 2001 Printed Circuit Odyssey", Circuit World, Vol. 27 No. 4. https://doi.org/10.1108/cw.2001.21727dab.006

Report on the Institute of Circuit Technology 27th Annual Symposium – 2001 Printed Circuit Odyssey

Report on the Institute of Circuit Technology 27th Annual Symposium – 2001 Printed Circuit Odyssey

It was inevitable that the title of Stanley Kubrick's 1968 science fiction classic would be the subject of some exploitation 33 years on. Amid an abundance of Odysseys this year, the ICTs "2001 Printed Circuit Odyssey", arguably justified the pun more than most.

But it was nothing like science fiction.

ICT Chairman, Steve Payne, introduced the 27th Annual Symposium programme with words like "journey" and "adventure", and the day was certainly long and exciting with eight excellent presentations illustrating the different directions in which printed circuit technology continues to advance in order to address the functional demands of the end user, and the considerations of the environment. In most cases the technology is pulled along a particular path by market trends and component packaging developments, but in a refreshing number of instances a spirit of innovation on the part of a few courageous researchers and far-sighted entrepreneurs is pushing it into new areas (see Plate 1).

Not everything is getting smaller. Gary Morse presented the first paper, which gave an insight into those issues, not least being a 4 billion dollar market opportunity, which drove APW to invest 21 million dollars in their Hedge End facility, dedicated to backplane manufacture and specialising in what Gary defined as "large format": typically 1,067mm x 788mm and up to 10mm thick, with up to 40 layers and 80,000 holes. Gary stressed that making such large circuits was not just a case of scaling-up existing equipment, since this tended to scale up the errors proportionally. There were many equipment design considerations and a lot of extra engineering was required if tolerances were to be maintained or, preferably, improved. There was a heavy emphasis on hands-off, flow-line operation with automated handling wherever possible, particularly as each multilayer panel could weigh up to 25kg, and with a 40-layer backplane containing over 30 square metres of inner layer image, a zero-defect philosophy was imperative if economic yields were to be achieved. Gary took the audience step-by-step through APW's manufacturing sequence, illustrating the equipment with clear photographs and explaining, for example, how a drilling machine would use two spindles simultaneously, not primarily to increase throughput but to minimise linear travel of the bed and hence reduce positional inaccuracy. One of life's realities was that even when special long-series drill bits are bought-in from the Far East 0.75mm is the smallest diameter available at the 12mm flute length needed to drill a 10mm-thick panel. Having drilled the holes, the next challenge was uniform through-plating distribution, particularly critical in backplanes whose assembly involves extensive use of press-fit connectors. APW had redefined "aspect ratio" by squaring the length dimension, to give more meaningful figures in the context of plating thickness control. For example, a 0.75mm hole in a 10mm panel would have aspect ratio of 133. Whatever the terminology, APW were able to achieve better than 1.5:1 surface-to-hole distribution in a two-hour cycle time using a carefully optimised pulse plating process.

Plate 1 Left to right: Alec Groves, Marconi; Stephen O'Reilly, NMRC; David Harrison, Brunel University; Steve Payne, ICT Chairman; Sue Pulko, The University of Hull, Narinder Bains, Shipley and Recipient of ICT David Kennedy Memorial Award; Gary Morse, APW Electronics, Martin Goosey, Shipley Europe and Paul Makin, Sigtronics

Alec Groves from British Aerospace Systems presented a paper entitled "A dream realisation", which illustrated the concept of producibility engineering in the development of a ten-layer mixed-substrate PTFE-FR4 multilayer circuit board for a next-generation radar system. In a programme extending over five years, which had so far involved more than 100 man-years of engineering effort, Alec described how the producibility engineer facilitated the complex interactions between designer, board fabricator and assembler through the strategy phase, the hardware design implementation phase and the build phase of the project. The focus was constantly on communication, and the project provided a definitive example of what can be achieved when the OEM takes the trouble to involve the PCB fabricator from the concept stage. Although the performance requirement demanded a very complex PCB substrate, proper discussion, cooperation and communication had resulted in a robust engineering solution which took into account all of the compromises which had to be made in choosing design parameters and manufacturing processes, together with the trade-offs between tolerances and yields, maintaining a balance between quality, performance, cost and timescale.

The actual dream realisation was evident in Alec's photograph of the technology-demonstrator radar system, standing in the Hebrides with 320 of the circuit boards in a fixed array, capable of tracking multiple targets and able to see a ballistic missile coming from 150 kilometres away!

Dr Stephen O'Reilly introduced his paper on "Integrated passives in printed wiring boards" by reviewing trends in the numbers of discrete passive components in mobile phones and personal computers. As numbers continue to increase and component miniaturisation is reaching a limit of practicality, integration of the devices into the substrate becomes an option worth serious consideration, with the potential benefits of freeing-up surface area, increasing reliability by reducing numbers of solder joints, shorter signal paths and lower assembly costs. Dr O'Reilly described his work at the National Microelectronics Research Centre in Cork on the COMPRISE project, funded as part of BriteEuRAM. Six other organisations were cooperating in the project: an OEM, a design house, a materials manufacturer, two PCB manufacturers, and the University of Hull. Dr O'Reilly described the materials and fabrication processes for integrated resistors, capacitors and inductors. Resistors were formed from a laminate with a nickel-phosphide layer under a conventional copper foil, using a two-stage image-and-etch process. Capacitors were formed by imaging and etching an FR4-type material which had a very thin dielectric layer (45 microns) of a high dielectric constant (about nine). Air-cored inductors were formed by imaging and etching spiral copper coils. For increased inductance, these could be laminated inside the circuit board and magnetic layers deposited on outer layers by electroplating nickel-iron alloy over an electroless nickel strike. By etching patterns to break up the continuity of the magnetic layer, losses could be reduced by disruption of eddy current effects.

Discussing the issues surrounding the applications of passive integration, Dr O'Reilly considered topics such as layout and CAD software, tolerancing, trimming and rework, reliability, thermal performance and testing. Full integration could not be cost-justified in all cases; an increasingly popular compromise was to go part-way by integrating components into arrays and networks. Future work would address issues of component interaction, cost analysis and design for manufacture, and technology demonstrators would be developed to assist in marketing the concept.

Another process with the potential to produce integrated components was described by Dr David Harrison. His team at Brunel University had applied the principles of offset lithography to the printing of conductive films, offering a means of producing "printed circuits" in the true sense of the term. Over the long term, the printing industry had demonstrated offset litho to be a low-cost, high throughput process capable of excellent resolution and registration. The objectives at Brunel were to produce high-resolution circuits with an energy-efficient process which avoided etching and the use of toxic materials. The work had been carried out on a small Heidelberg press, using a silver-based ink which gave a deposit thickness between 3 and 5 microns. Track widths of 80 microns with gaps of 40 microns had already been achieved in high yield, and encouraging results had been seen at 60 micron track width. The technique was potentially capable of printing 10 micron tracks.

Resistors had been produced with repeatability to within +/–2.5 percent, capacitors were formed by printing interdigitated patterns, and a novel application was the printing of polymer LEDs on paper or polyester. The example Dr Harrison demonstrated was perhaps not the brightest of displays, but certainly proved the principle!

The conductive lithographic film technique offered scope for seeding of electroless plating, and Brunel had worked with Shipley to develop a procedure. Although it had been necessary to modify the ink formulation to improve adhesion and to avoid poisoning of the plating chemistry, the exercise had resulted in a commercially viable process for the high-speed, low-cost production of polyester-based flexible circuits, which had been patented and licensed to a PCB manufacturer in Scotland. The whole programme of conceiving a technique, developing a process, patenting it and licensing it out had taken place within a five-year time-frame.

Narinder Bains, a research technologist from Shipley, collected the David Kennedy Memorial Award for his contribution to the PRIME project. David Kennedy, a founder member of the ICT. and a past chairman of the PCIF, had always been committed to encouraging the education and training of young people within the industry, and Mrs Valerie Kennedy presented the award in his memory (see Plate 2).

Narinder gave a progress report on the PRIME project, a collaborative exercise involving six European companies with interests in PCB manufacturing and electronics packaging, aimed at developing an environmentally-friendly process for high density interconnection, based on laser-activatable dielectric materials. The design rule parameters of 75 micron lines and spaces, 75 micron holes in 150 micron lands and 100 micron dielectric thicknesses had been achieved by a process sequence involving laser machining of slots and vias followed by selective full-build metallisation with an accelerated electroless copper. The copper deposited selectively on the laser-ablated areas, eliminating the need for photoresists or tin-lead pattern plating. Two alternative routes were available using either a catalysed substrate, or a catalytic coating on a conventional substrate. For catalysed substrated, the activation mechanism was the formation of oxygen vacancies in a filler material as a consequence of laser ablation. Of several catalytic fillers and laser wavelengths evaluated, the best results so far had been observed using a titanium dioxide filler in combination with a 248nm KrF excimer laser.

Plate 2 Valerie Kennedy presents ICT David Kennedy award to Narinder Bains

A palladium-based catalytic coating, applied by spray, dip or spin coating, and selectively activated by laser, was the process alternative. However, its negative-working characteristics made it unsuitable for through-hole applications, and its high material cost and limited hold-time made this the less attractive option. An important part of the project had been the development of a high-speed full-build electroless copper process combining ease of control with improved adhesion and ductility. The reulting CP4750 process was used in a two-stage sequence, initially at 458C as a 1.5 micron strike, then to 15 microns in four hours at 60°C.

The afternoon session began with an exceptionally well-presented paper from Dr Sue Pulko of the University of Hull, another partner in the COMPRISE project. To complement Dr O'Reilly's earlier account of applications of integrated components, Dr Pulko described the development of a technique for the three-dimensional numerical simulation of thermal effects of embedded passive components. It was now possible to model the temperature distribution resulting from the heat generated by embedded devices for a range of different circuit constructions, and the technique had been used to study trends and interactions within a layer and between layers. Temperature coefficient of resistance had been used as an elegant means of measuring device temperatures, and a good correlation had been observed between predicted and actual values. A set of rules had been derived to enable the accurate prediction of thermal effects and an effective design tool was now available which, once the location of heat-generating components had been input, could display the temperature distribution graphically, as a series of contour plots.

In a paper entitled "Prototype PCBs in hours with additive copper polymer technology", Paul Makin described how, out of frustration at not being able to source prototype circuits quickly or cost-effectively, the founders of Sigtronics had devised their own novel process, which, with the help of government grants and local awards, they had developed into a self-contained prototyping machine.

Their "Quickboard" system had won the John Logie Baird Award for innovation, and enabled the manufacture of double sided circuits with through-hole connections within a few hours. The principle of operation was direct imaging by mechanical engraving of the circuit pattern on unclad FR4 laminate then filling the pattern with a heat-cured copper paste. Through connections were formed using plugged vias, which could be drilled out for component insertion if necessary. The conductors exhibited low resistance and good solderability. The whole manufacturing operation took place inside a single unit measuring 1,500mm x 1,500mm x 1,000mm, which contained the engraving machine, the wiping mechanism for application of the paste, and an inert-atmosphere curing oven, together with all the controls and operating software, all powered from a 13 amp plug. In development was a system based on laser-engraving for increased speed and finer resolution.

Rounding-off the day, ICT Council member and Circuit World Editor, Dr Martin Goosey gave delegates a glimpse into the future from a materials perspective. Demands for processing power, transmission frequency, bandwidth and memory were taking existing materials beyond their effective limits, and a new generation of materials and enabling technologies was needed. It was predicted that by 2005, processor speed would be approaching the terabits per second level, with memory measured in terabytes, and that within the next 20 years the world electronics industry would have grown to four times its present size. Driven by the demand for bandwidth, applications of optoelectronics were rapidly gathering momentum and packaging and interconnection technologies were working towards "getting the light closer to the chip", with optical interconnection systems incorporating waveguides and optical vias within the circuit board. Materials would be required which did not absorb at the operating wavelengths of 830nm, 1,300nm and 1,500nm, and these would probably be organics with low loss and thermal stability. New materials would also be needed to enable semiconductor devices to operate faster. Copper was beginning to replace aluminium, in conjunction with materials of lower dielectric constant than silicon dioxide, in order to minimise the cumulative effects of gate delays and interconnect delays in high speed devices. There was also increasing use of chemical-mechanical planarisation techniques in the production of silicon, to enable the printing of increasingly finer features. Referring to the earlier presentations on embedded passive components, Dr Goosey remarked that we would soon be seeing active components embedded within circuit boards.

As Steve Payne had promised, the 27th ICT Annual Symposium was a day of adventures and journeys into the future. Perhaps not as far out as the 1968 film reviewers would have had us believe: "2001: A Space Odyssey is a countdown to tomorrow, a road map to human destiny, a quest for the infinite". Maybe if Steve had played Also Sprach Zarathrustra as background music ...

Pete StarkeyICT Committee Member