RETRACTED: Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA
International Journal of Pervasive Computing and Communications
ISSN: 1742-7371
Article publication date: 26 August 2021
Issue publication date: 18 February 2022
Retraction statement
The publishers of International Journal of Pervasive Computing and Communications, wish to retract the article S.B., S. and M. Sandi, A. (2022), “Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA”, International Journal of Pervasive Computing and Communications, Vol. 18 No. 2, pp. 250-265. https://doi.org/10.1108/IJPCC-05-2021-0115
An internal investigation into a series of submissions has uncovered evidence that the peer review process was compromised. As a result of these concerns, the findings of the article cannot be relied upon. This decision has been taken in accordance with Emerald's publishing ethics and the COPE guidelines on retractions.
Despite numerous attempts to contact the authors, the journal has received no response; the response of the authors would be gratefully received.
The publishers of the journal sincerely apologize to the readers.
Abstract
Purpose
The small area network for data communication within routers is suffering from storage of packet, throughput, latency and power consumption. There are a lot of solutions to increase speed of commutation and optimization of power consumption; one among them is Network-on-chip (NoC). In the literature, there are several NoCs which can reconfigurable dynamically and can easily test and validate the results on FPGA. But still, NoCs have limitations which are regarding chip area, reconfigurable time and throughput.
Design/methodology/approach
To address these limitations, this research proposes the dynamically buffered and bufferless reconfigurable NoC (DB2R NoC) using X-Y algorithm for routing, Torus for switching and Flexible Direction Order (FDOR) for direction finding between source and destination nodes. Thus, the 3 × 3 and 4 × 4 DB2R NoCs are made free from deadlock, low power and latency and high throughput. To prove the applicability and performance analysis of DB2R NoC for 3 × 3 and 4 × 4 routers on FPGA, the 22 bits for buffered and 19 bit for bufferless designs have been successfully synthesized using Verilog HDL and implemented on Artix-7 FPGA development bond. The virtual input/output chips cope pro tool has been incorporated in the design to verify and debug the complete design on Artix-7 FPGA.
Findings
In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.
Originality/value
In the obtained result, it has been found that 35% improvement in throughput, 23% improvement in latency and 47% optimization in area has been made. The complete design has been tested for 28 packets of injection rate 0.01; the packets have been generated by using NLFSR.
Keywords
Citation
S.B., S. and M. Sandi, A. (2022), "RETRACTED: Design and analysis of buffer and bufferless routing based NoC for high throughput and low latency communication on FPGA", International Journal of Pervasive Computing and Communications, Vol. 18 No. 2, pp. 250-265. https://doi.org/10.1108/IJPCC-05-2021-0115
Publisher
:Emerald Publishing Limited
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