Reliability evaluation and modeling of high density electronic packages

Abstract

Purpose

The purpose of this paper is to describe key failure mechanisms observed during the development of the advanced packaging technology. Extensive accelerated stress tests are conducted to collect failure data and understand failure characteristics and failure trends. The results will be useful for design improvement and failure rate predictions.

Design/methodology/approach

High density chip scale packages (CSP) are developed to meet the needs for high performance and small form‐factor products, but with reduced process procedures and product cost. Test‐to‐failure approaches are applied to evaluate the failure rate and reliability models instead of compliance qualification testing approaches.

Findings

The study shows Cu‐trace cracking failure can be treated as random failures and analyzed using a constant failure rate approach. The acceleration factor for the Cu‐trace cracking failure mechanism exhibits a large power exponent comparing to the parameters used in reference models. In addition, the solder joint failure data collected through the study do not fit well with the well‐known solder fatigue life model. Moreover, the test results affirm the test‐to‐failure approach adopted in data collection is providing more accurate failure characteristics compared to the compliance qualification testing approach.

Practical implications

The paper shows that the reliability performance of package technology can be improved by enhancing the package design, improving manufacturing processes and materials optimization.

Originality/value

This is an original research paper and the test‐to‐failure approach in the reliability study helps provide realistic reliability predictions.

Citation

Yang, L. and Bernstein, J. (2012), "Reliability evaluation and modeling of high density electronic packages", Microelectronics International, Vol. 29 No. 1, pp. 15-21. https://doi.org/10.1108/13565361211219121