Parity information placement in the disk array model

Abstract

Purpose

The primary purpose of this paper is to explore possible locations for parity cache within disk array model and describe the disk array model development process.

Design/methodology/approach

A dynamic, discrete event simulation model, based on modular, bottom‐up approach, is initiated from a single disk, and then extended on disk array.

Findings

Parity information within array model cannot be stored on individual disk cache, instead it should be stored in array cache. If model is used for simulation of single disk array then an approach with separate parity cache should be used, while an approach where a parity cache is part of array cache should be used for simulation of more complex storage systems with numerous arrays.

Research limitations/implications

The proposed model does not include any read‐ahead cache policy, and only a full‐stripe writes can be performed. As a result, the model should be used only for sequential read or write of large files because then those limitations do not influence simulation output.

Originality/value

The novelty depicted in this paper is an approach, in array modelling, with parity cache merged into array cache. Also, the achieved bandwidth for the resulting simulation model differs from 1.05 to 1.7 per cent from the measured one on the experimental array.

Citation

Vicković, L., Mudnić, E. and Gotovac, S. (2009), "Parity information placement in the disk array model", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 28 No. 6, pp. 1428-1441. https://doi.org/10.1108/03321640910991994