Low‐power noise multilayer PCB with discrete decoupling capacitors inside

Abstract

Purpose

The purpose of this paper is to present the power noise characteristics of a multilayer printed circuit board (PCB) in which discrete capacitors have been embedded.

Design/methodology/approach

Embedded technology has been implemented on a multilayer PCB to enhance the performance and functionality and to decrease the power noise. Decoupling capacitors were directly positioned on the inner power planes of a board, which resulted in low‐loop inductance through the minimized length of the interconnection from the chips to the PCB's power delivery network.

Findings

A low‐noise PCB was successfully designed and fabricated using an embedding process for the discrete decoupling capacitors. It was demonstrated that such an approach offers lower interconnection inductance and quiet noise performance, including highly efficient propagation noise suppression at wideband frequencies.

Research limitations/implications

Most conventional simulation techniques offer expectations for the signal characteristics on the time domain to minimize bit error rates in application systems. Further development work will focus on the integrated simulation models including the equivalent circuits for the transmission line and power noise effects to improve the accuracy of the signal performance.

Originality/value

This paper presents a new approach for improving generating and propagating noise performance through the use of an embedded decoupling capacitor design methodology.

Citation

Song, K., Kim, J., Yoo, J., Nah, W., Lee, J. and Sim, H. (2009), "Low‐power noise multilayer PCB with discrete decoupling capacitors inside", Circuit World, Vol. 35 No. 2, pp. 30-36. https://doi.org/10.1108/03056120910953295